Title :
A parallel approach for testing multi-port static random access memories
Author :
Karimi, F. ; Irrinki, S. ; Crosbuy, T. ; Lombardi, E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells
Keywords :
SRAM chips; integrated circuit testing; logic testing; parallel processing; random-access storage; coupling faults; embedded memories; inter-port fault detection; memory chips; memory. partitioning; multiport SRAM; multiport memories; parallel testing approach; parallelization; port assignment process; shorts; static random access memories; Communication switching; Fault detection; Logic; Manufacturing processes; Microprocessors; Read-write memory; Switches; System testing; System-on-a-chip; Wide area networks;
Conference_Titel :
Memory Technology, Design and Testing, IEEE International Workshop on, 2001.
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1242-9
DOI :
10.1109/MTDT.2001.945233
