An adaptive scheme for bus error detection

Author

Ge Chen ; Nooshabadi, Saeid

Author_Institution

Sch. of EE & Telecom, Univ. of New South Wales, Sydney, NSW, Australia

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

Bus interconnection on deep submicron (DSM) technologies incur significantly larger power dissipation due to coupling capacitance between adjacent bus wire. This paper proposed an adaptive driver scheme to adjust the voltage on the wire in real time according to number of errors detected on a dedicated sensitive wire. Energy cost on the long interconnection can be reduced without the degradation in the noise performance. Specifically, for an 8-bit and 16-bit buses in 65 nm CMOS technology, we present a solution that reduces the energy dissipation and achieve similar noise performance.

Keywords

CMOS integrated circuits; capacitance; integrated circuit interconnections; CMOS technology; bus error detection; bus interconnection; bus wire; coupling capacitance; deep submicron technologies; energy dissipation; power dissipation; size 65 nm; word length 16 bit; word length 8 bit; Adaptation models; Bit error rate; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026652

Filename

6026652