DocumentCode :
3409040
Title :
On generating test sets that remain valid in the presence of undetected faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
1997
fDate :
13-15 Mar 1997
Firstpage :
20
Lastpage :
25
Abstract :
We consider the problem of generating tests for single stuck-at faults that remain valid in the presence of undetected single stuck-at faults. We show that enumeration of all subsets of faults that may occur in the circuit without being detected may be too computation intensive, and is not necessary to obtain high-quality test sets. We present a test generation procedure to generate tests that remain valid in the presence of undetected faults. The procedure targets simultaneously multiple subsets of undetected faults that may be present in the circuit. It thus allows test generation time to be minimized by allowing the number of subsets of faults considered explicitly to be minimized. Based on this test generation procedure, several approximate procedures are also explored
Keywords :
fault diagnosis; integrated circuit testing; logic testing; approximate procedures; high-quality test sets; multiple fault subsets; single stuck-at faults; test generation time minimization; test set generation; undetected single stuck-at faults; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Fault diagnosis; Manufacturing; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
Conference_Location :
Urbana-Champaign, IL
ISSN :
1066-1395
Print_ISBN :
0-8186-7904-2
Type :
conf
DOI :
10.1109/GLSV.1997.580405
Filename :
580405
Link To Document :
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