• DocumentCode
    3409095
  • Title

    A fast algorithm for locating and correcting simple design errors in VLSI digital circuits

  • Author

    Veneris, Andreas G. ; Hajj, Ibrahim N.

  • Author_Institution
    Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
  • fYear
    1997
  • fDate
    13-15 Mar 1997
  • Firstpage
    45
  • Lastpage
    50
  • Abstract
    With the increase in the complexity of VLSI circuit design and the corresponding increase in the number of logic gates on a chip, logic design errors can frequently occur. In this paper we present an efficient approach to Design Error Detection and Correction when a small number of modifications can rectify the design. Our method is based on test vector simulation and Boolean function manipulation techniques. The proposed approach guarantees to return a solution, if such a solution exists in our modification model, in a short computational time. Experimental results show the robustness of our approach
  • Keywords
    Boolean functions; VLSI; combinational circuits; digital integrated circuits; error correction; error detection; fault diagnosis; integrated circuit design; logic CAD; logic design; logic testing; Boolean function manipulation techniques; VLSI digital circuits; combinational circuits; design error correction; design error location; fast algorithm; logic design errors; modification model; robustness; short computational time; test vector simulation; Algorithm design and analysis; Boolean functions; Circuit synthesis; Circuit testing; Computational modeling; Error correction; Logic circuits; Logic design; Logic gates; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
  • Conference_Location
    Urbana-Champaign, IL
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-7904-2
  • Type

    conf

  • DOI
    10.1109/GLSV.1997.580409
  • Filename
    580409