A new low-voltage full adder circuit

Author

Lee, Hanho ; Sobelman, Gerald E.

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1997

fDate

13-15 Mar 1997

Firstpage

88

Lastpage

92

Abstract

A new circuit based on combining XOR gates and double pass-transistor logic has been developed for implementing a full adder. The main design objectives for these new circuits are low power consumption and full-voltage swing at a low supply voltage. The proposed full adder circuit is compared with previously known circuits and is shown to provide superior performance. The new and previous full adder circuits have been fully simulated using HSPICE with 0.4 μm CMOS technology at a 2.0 V supply voltage. An extensive analysis of a 8-bit carry-select adder establishes the superiority of the proposed circuit in that application

Keywords

CMOS logic circuits; VLSI; adders; delays; digital arithmetic; integrated circuit design; logic design; 0.4 micron; 2 V; CMOS technology; HSPICE simulation; LV full adder circuit; XOR gates; carry-select adder; double pass-transistor logic; full-voltage swing; low power consumption; low-voltage operation; Adders; Batteries; CMOS technology; Circuit simulation; Circuit synthesis; Digital signal processing; Energy consumption; Equations; Low voltage; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on

Conference_Location

Urbana-Champaign, IL

ISSN

1066-1395

Print_ISBN

0-8186-7904-2

Type

conf

DOI

10.1109/GLSV.1997.580416

Filename

580416