A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology

After analyzing the advantages and disadvantages of all the general algorithms adopted now in designing square root calculators on FPGA chips with pipeline technology, a new algorithm is proposed based on the relationship between increment and remainder and then its principle is analyzed in details in the paper. The algorithm is realized on the Quartus2 development platform with Verilog HDL language and the flow chart which implements the algorithm is given .The simulation results show that it is characterized by occupying less resource and processing in a faster speed as well as being easier to implement. Therefore it is an effective algorithm for implementing square root calculators on commonly-used FPGA chips with pipeline technology.