A PVT-tolerant, ultra-low-power phase-locked loop for wireless implantable biomedical devices

An ultra-low-power, low-voltage frequency synthesizer designed for implantable biomedical devices is presented. Several design techniques are employed to address the issues in ultra-low voltage design, including the dynamic threshold-voltage for a drain-switching charge pump and dual resistor-varactor tuning for a ring-based voltage control oscillator. Moreover, three automatic calibration circuits are embedded to compensate the performance deviation due to process-voltage-temperature (PVT) variations. Designed in 0.13-μm CMOS technology with a power supply of 0.5 V, the PLL consumes 370 μW with a phase noise of -104 dBc/Hz at 1 MHz offset.