VLSI architectures for programmable sorting of analog quantities with multiple-chip support

The paper describes VLSI architectures for sorting analog quantities. The elementary circuit unit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design and enables multi-chip integration. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors