A multiple shared memory switch

One of the problems that shared memory switches have is that in order to build large switches the memory access requirements become stringent. One way to overcome this is to utilize multiple buffers which space division multiplex the input lines and thereby alleviate the memory access requirements. However, previous attempts to implement multi-buffered shared memory switches have suffered from serious limitations. The authors describe in this work a multi-buffered architecture that offers tremendous potential. It is able to fully share the buffer, it guarantees the minimum delay switching of all cells, it can accomplish multi-cast and multi-channel switching, it can accommodate various priorities and classes of traffic while maintaining high performance on account of very efficient buffer utilization