DocumentCode
3409732
Title
Bit Flipping-Sum Product Algorithm for regular LDPC codes
Author
Alami, R.E. ; Gueye, C.B. ; Boussetta, M. ; Zouak, M. ; Mrabti, M.
Author_Institution
LESSI, Fac. des Sci. Dhar Mehraz, Fez, Morocco
fYear
2010
fDate
Sept. 30 2010-Oct. 2 2010
Firstpage
1
Lastpage
4
Abstract
In this paper we present Low Density Parity Check decoding algorithm that assemble two different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product Algorithm (BFSP). To reduce the bit error rate, we perform the Bit-Flipping algorithm after the Sum-Product algorithm. Simulation results over an additive white Gaussian channel show that the error performance of a LDPC codes with Bit Flipping-Sum Product decoding is within 0.2 dB of the standard Sum-Product decoding algorithms. Furthermore, the decoding complexity of the proposed BFSP algorithm is maintained at the same level as that of the standard Sum-Product algorithm.
Keywords
AWGN channels; error statistics; parity check codes; additive white Gaussian channel; bit error rate; bit flipping; low density parity check decoding algorithm; regular LDPC codes; sum product algorithm; AWGN; Bit error rate; Decoding; Iterative decoding; Signal to noise ratio; Simulation; Low-density-parity-check codes; bit error rate; bit-flipping; sum-product;
fLanguage
English
Publisher
ieee
Conference_Titel
I/V Communications and Mobile Network (ISVC), 2010 5th International Symposium on
Conference_Location
Rabat
Print_ISBN
978-1-4244-5996-4
Type
conf
DOI
10.1109/ISVC.2010.5656207
Filename
5656207
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