A low-leakage dynamic multi-ported register file in 0.13 μm CMOS

Author

Alvandpour, Atila ; Krishnamurthy, Ram ; Soumyanath, K. ; Borkar, Shekhar

Author_Institution

Microprocessor Res. Labs, Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

2001

Firstpage

68

Lastpage

71

Abstract

Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256×32b 4-read/write-port register-file for ~6 GHz operation at 1.2 V in a 0.13 μm technology. The pre-charged local bit-lines utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Using this technique, we are able to improve upon all-low-Vt performance by 4%, while maintaining dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5×

Keywords

CMOS logic circuits; VLSI; integrated circuit noise; leakage currents; sequential circuits; shift registers; 0.13 micron; 1.2 V; 32 bit; 6 GHz; CMOS; active leakage power; conditional keeper-technique; dual-Vt usage; dynamic output; leakage currents; low-leakage dynamic multi-ported register file; noise margins; pre-charged local bit-lines; Circuit noise; Clocks; Degradation; Delay; Leakage current; Microprocessors; Noise reduction; Noise robustness; Phase noise; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, International Symposium on, 2001.

Conference_Location

Huntington Beach, CA

Print_ISBN

1-58113-371-5

Type

conf

DOI

10.1109/LPE.2001.945375

Filename

945375