Title :
Theory and practical implementation of harmonic resonant rail driver
Author :
Moon, Joong-Seok ; Athas, William C. ; Beerel, Peter A.
Author_Institution :
Univ. of Southern California, Los Angeles, CA, USA
Abstract :
This paper presents a new algorithm for designing efficient harmonic resonant rail drivers. The circuit solution is coupled to a standard pulse source and uses only discrete passive components. It can thus be externally tuned to minimize the consumed power in the target IC. A new efficient algorithm based on current-fed pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed driver topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonies of the desired waveform, however, this paper focuses on the generation of square-wave clock signals. We have tested the driver with a capacitive load between 38.3 pF and 97.8 pF. The overall dissipation for our second-order harmonic rail driver is 19% of fCV2 at 15 MHz and 97.8 pF load
Keywords :
CMOS digital integrated circuits; VLSI; circuit resonance; driver circuits; harmonics; low-power electronics; square-wave generators; timing circuits; 15 MHz; 38.3 to 97.8 pF; clock generation; current-fed pulse-forming network theory; design algorithm; energy-recovery circuit; harmonic resonant rail drivers; multiple harmonics supposition; periodic waveform generation; square-wave clock signals; Algorithm design and analysis; Capacitance; Coupling circuits; Driver circuits; Frequency; Network topology; Pulse circuits; Rails; Resonance; Signal generators;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945392
