Title :
Programmable hybrid co-processor for real-time image understanding
Author :
Erten, Gamze ; Salam, Fathi M.
Author_Institution :
IC Tech. Inc., Okemos, MI, USA
fDate :
Oct. 30 1995-Nov. 1 1995
Abstract :
A novel hybrid image co-processor architecture that utilizes analog and digital computing techniques cooperatively is described. The chip computes stereo and motion correspondence at a rate of 30 frames/sec. This feature combined with programmable capabilities of a conventional processor makes it possible to execute in real-time many powerful yet so far underutilized computing techniques such as multiresolution or image pyramid processing. The overall system is designed to be compatible with existing computer architectures to allow for commercial product development in the near future. Additional benefits of the system over existing image processing methods are multiple programmable configurations, increased processing speed, low power consumption, reduced size and cost.
Keywords :
image resolution; analog VLSI; analog computing techniques; commercial product development; computer architectures; digital computing techniques; edge detection; hybrid image coprocessor architecture; image convolution; image processing methods; image pyramid processing; low power consumption; motion correspondence; multiple programmable configurations; multiresolution; neuronal visual processing; processing speed; programmable hybrid coprocessor; real-time image understanding; reduced cost; reduced size; stereo correspondence; Analog computers; Analog integrated circuits; Cameras; Computer architecture; Computer vision; Coprocessors; Digital integrated circuits; Image processing; Layout; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7370-2
DOI :
10.1109/ACSSC.1995.540827
