An architecture of highly parallel computer AP 1000

Author

Ishihata, Hiroaki ; Horie, Toshihiro ; Inano, Satoshi ; Shimizu, Toshiyuki ; Kato, Sadayuki

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

1991

fDate

9-10 May 1991

Firstpage

13

Abstract

A highly parallel computer with distributed memory called the AP1000 has been developed. The system consists of 64 and 1024 processing elements and three independent networks called the torus network (T-net), broadcast network (B-net), and synchronization network (S-net). The design goal for the AP1000 is to attain low-latency, high-throughput communication. To reduce the overall communication latency, a message controller and a new routing scheme on the T-net have been developed. The design concepts, architecture, and some results from performance tests for the AP1000 are presented

Keywords

parallel architectures; parallel machines; AP 1000; architecture; broadcast network; design; distributed memory; highly parallel computer; low-latency high-throughput communication; message controller; routing scheme; synchronization network; torus network; Broadcasting; Communication networks; Communication system control; Computer architecture; Concurrent computing; Delay; Distributed computing; Routing; System recovery; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-87942-638-1

Type

conf

DOI

10.1109/PACRIM.1991.160669

Filename

160669