Energy-efficient instruction dispatch buffer design for superscalar processors

Author

Kucuk, Gurhan ; Ghose, Kanad ; Ponomarev, Dmitry V. ; Kogge, Peter M.

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA

fYear

2001

fDate

2001

Firstpage

237

Lastpage

242

Abstract

The instruction dispatch buffer (DB, also known as an issue queue) used in modem superscalar processors is a considerable source of energy dissipation. We consider design alternatives that result in significant reductions in the power dissipation of the DB (by as much as 60%) through the use of: (a) fast comparators that dissipate energy mainly on a tag match, (b) zero byte encoding of operands to imply the presence of bytes with all zeros and, (c) bitline segmentation. Our results are validated by the execution of SPEC 95 benchmarks on true hardware level, cycle-by-cycle simulator for a superscalar processor and SPICE measurements for actual layouts of the DB and its variants in a 0.5 micron CMOS process

Keywords

CMOS digital integrated circuits; SPICE; buffer circuits; comparators (circuits); instruction sets; integrated circuit design; low-power electronics; microprocessor chips; 0.5 micron; CMOS circuit; SPICE; bitline segmentation; comparator; cycle-by-cycle simulator; energy efficiency; instruction dispatch buffer; issue queue; low-power design; power dissipation; superscalar processor; zero byte encoding; Computer science; Encoding; Energy dissipation; Energy efficiency; Hardware; Logic; Permission; Power dissipation; Process design; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, International Symposium on, 2001.

Conference_Location

Huntington Beach, CA

Print_ISBN

1-58113-371-5

Type

conf

DOI

10.1109/LPE.2001.945407

Filename

945407