A runtime verification monitoring approach for embedded industrial controllers

Complexity in industrial control systems has grown exponentially during the past decade. The reliability of such systems is dependant on trustable embedded controllers. The design of such embedded controllers is moving towards reliability-centric hardware/software co-design frameworks. This paper proposes a novel approach to the development of such embedded controllers, by proposing a special embedded monitoring scheme. An experimental evaluation framework is described that supports runtime verification of a software application executing in an embedded system, where the processor is a Java Optimised Processor (JOP) soft processor, instantiated in the fabric of an FPGA (field programmable gate array). The experimental system employs the Java-MaC (Java Monitoring and Checking) runtime verification method, arranged to indirectly monitor the execution behaviour of the application software in its native environment. A case study example is described, which demonstrates the verification of a condition for a software model of a railroad crossing system. The example shows that such a runtime verification scheme can be used effectively as a software testing approach for such a specialised embedded controller. The issues of how to minimise the overhead impact of the monitoring scheme and how to provide an interface for the monitor are considered.