Title :
A low power based system partitioning and binding technique for multi-chip module architectures
Author :
Cherabuddi, R.V. ; Bayoumi, M.A. ; Krishnamurthy, H.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs
Keywords :
circuit layout CAD; high level synthesis; integrated circuit interconnections; logic partitioning; multichip modules; stochastic processes; MCM; benchmark designs; binding technique; functional units; high-level synthesis framework; inter-chip buses; multi-chip module architectures; stochastic evolution based technique; switching activity; system partitioning; Capacitance; Circuit synthesis; Communication switching; Data flow computing; Frequency; High level synthesis; Minimization methods; Power dissipation; Signal synthesis; Switching circuits;
Conference_Titel :
VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
Conference_Location :
Urbana-Champaign, IL
Print_ISBN :
0-8186-7904-2
DOI :
10.1109/GLSV.1997.580530
