• DocumentCode
    3410480
  • Title

    Minimizing error and VLSI complexity in the multiplication free approximation of arithmetic coding

  • Author

    Feygin, Gennady ; Gulak, P. Glenn ; Chow, Paul

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
  • fYear
    1993
  • fDate
    1993
  • Firstpage
    118
  • Lastpage
    127
  • Abstract
    Two new algorithms for performing arithmetic coding without multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst-case normalized excess length to under 0.8% versus 1.911% for the previously known best method of Chevion et al. The second algorithm, suitable only for alphabets of less than twelve symbols, allows even greater reduction in the excess code length. For the important binary alphabet the worst-case excess code length is reduced to less than 0.1% versus 1.1% for the method of Chevion et al. The implementation requirements of the proposed new algorithms are discussed and shown to be similar
  • Keywords
    VLSI; coding errors; minimisation; VLSI complexity; algorithms; arithmetic coding without multiplication; binary alphabet; error; excess code length; implementation requirements; Computer errors; Data compression; Digital arithmetic; Encoding; Iterative decoding; Iterative methods; Registers; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Data Compression Conference, 1993. DCC '93.
  • Conference_Location
    Snowbird, UT
  • Print_ISBN
    0-8186-3392-1
  • Type

    conf

  • DOI
    10.1109/DCC.1993.253138
  • Filename
    253138