Title :
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools
Author :
Hirabayashi, Masayuki ; Nose, Koichi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
Abstract :
Design methodology for dual-VTH scheme using commercially available tools is presented and optimization strategy for the dual-VTH scheme is discussed. In order to suppress the power consumption, it is shown that using library cells that have various combinations of VTH´s is not needed. The cell library, which contains logic gates with all high VTH transistors and all low VTH transistors, is sufficient to reduce leakage power. 0.1 V is shown to be the optimum value for VTH difference between VTH,HIGH and VTH,LOW in terms of power reduction
Keywords :
VLSI; circuit CAD; circuit optimisation; integrated circuit design; leakage currents; low-power electronics; CAD tool; VLSI circuit; cell library; design optimization; dual-threshold voltage method; leakage current; logic gate; low-power design; power consumption; Circuits; Delay; Design methodology; Design optimization; Leakage current; Libraries; Nose; Permission; Threshold voltage; Very large scale integration;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945418
