Parallel VLSI architectures for cryptographic systems

Author

Ancona, Fabio ; Gloria, Alessandro De ; Zunino, Rodolfo

Author_Institution

Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy

fYear

1997

fDate

13-15 Mar 1997

Firstpage

176

Lastpage

181

Abstract

This paper describes a parallel VLSI implementation of a private-key cryptographic system based on Peano-Hilbert curves. The basic unit of the VLSI architecture is the Crypto Processor, that is an SIMD composed of a grid of 256×256 processing units performing elementary operations of encoding process. The key length of the system, measured as number of free parameters, depends linearly on hardware complexity: the cryptographic system is modular and its implementation is very cheap. The CP has been implemented as a single chip with a 1-micron CMOS technology and shows a working frequency of 30 MHz. The chip can be used in consumer applications as well as add-on whenever a certain degree of safety in communication is required

Keywords

CMOS digital integrated circuits; VLSI; cryptography; microprocessor chips; parallel architectures; 30 MHz; CMOS technology; Peano-Hilbert curves; SIMD; consumer applications; crypto processor; encoding process; free parameters; hardware complexity; parallel VLSI architectures; private-key cryptographic system; CMOS technology; Encoding; Fractals; Hardware; Polynomials; Public key; Public key cryptography; Safety; Semiconductor device measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on

Conference_Location

Urbana-Champaign, IL

ISSN

1066-1395

Print_ISBN

0-8186-7904-2

Type

conf

DOI

10.1109/GLSV.1997.580537

Filename

580537