Title :
Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing
Author :
Adaos, K.D. ; Alexiou, G.P. ; Kanopoulos, N.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
Abstract :
In this paper we present an efficient implementation of a serial/parallel two´s complement multiplication scheme. The proposed implementation, provided in register transfer level VHDL code, can be synthesized to a variety of FPGA and ASIC technologies. Experimental results based on industry tools verify the efficiency of the multiplier in terms of speed and area. The proposed implementation can be used as a building block for intellectual property (IP) based development and rapid prototyping of VLSI digital signal processing systems
Keywords :
VLSI; application specific integrated circuits; circuit CAD; digital signal processing chips; field programmable gate arrays; hardware description languages; industrial property; integrated circuit design; multiplying circuits; rapid prototyping (industrial); ASIC technologies; FPGA; IP based development; VLSI digital signal processing; area; intellectual property; rapid prototyping; register transfer level VHDL code; serial/parallel multiplier; speed; two´s complement multiplication scheme; Application specific integrated circuits; Digital signal processing; Field programmable gate arrays; Guidelines; Prototypes; Signal design; Signal processing; Signal processing algorithms; Signal synthesis; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812217
