Optimum double-layer spiral inductor on silicon substrate designed for monolithic buck converters

An optimum design strategy of double-layer square spiral inductor for the monolithic low-voltage, low-power buck converter operating at 100MHz is presented. After optimization using 0.35μm standard CMOS technology, the inductor with inductance of 24.74nH, Q factor of 8.43 and occupied area 0.19 square millimeters is achieved. A simple circuit model is given to simulate the performance of the buck converter. From the simulation results, the designed double-layer spiral inductor can satisfy the requirement.