A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology

Author

Lee, Seungjae ; Lee, Young-Taek ; Han, Wook-Kee ; Kim, Dong-Hwan ; Kim, Moo-Sung ; Moon, Seung-Hyun ; Cho, Hyun Chul ; Lee, Jung-Woo ; Byeon, Dae-Seok ; Lim, Young-Ho ; Kim, Hyung-Suk ; Hur, Sung-Hoi ; Suh, Kang-Deog

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

52

Abstract

A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.

Keywords

CMOS memory circuits; NAND circuits; PLD programming; flash memories; integrated circuit noise; microprogramming; 1 bit; 1.6 Mbit/s; 2 Gbit; 2 bit; 3.3 V; 4 Gbit; 90 nm; CMOS technology; cell array; cell threshold voltage distribution; coupling noise; floating poly thickness; four-level NAND flash memory; fuse-bonding; pad-bonding; program operation; program throughput; program-after-erase technique; rise time; row decoder; simultaneous data load; Buffer storage; CMOS technology; Costs; Decoding; Explosives; Flash memory; Home appliances; Moon; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332589

Filename

1332589