Design and implementation of the POWER5™ microprocessor

Author

Clabes, J. ; Friedrich, J. ; Sweet, Mark ; DiLullo, J. ; Chu, S. ; Plass, Donald ; Dawson, John ; Muench, Paul ; Powell, Louie ; Floyd, Melissa ; Sinharoy, B. ; Lee, Minhung ; Goulet, Mathieu ; Schwartz, N. ; Gorman, G. ; Restle, Phillip ; Kalla, R. ; McG

Author_Institution

IBM, Austin, TX, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

56

Abstract

POWER5 offers ∼4× performance over the previous design by incorporating simultaneous multithreading, a latency-optimized memory subsystem, extensive reliability, availability and serviceability (RAS), and power management support. The 276M-transistor processor is implemented in a 0.13 μm, 8M silicon-on-insulator technology and operates above 1.5 GHz.

Keywords

integrated circuit design; integrated circuit measurement; integrated circuit reliability; microprocessor chips; multi-threading; silicon-on-insulator; 0.13 micron; 1.5 GHz; POWER5 microprocessor; RAS; Si-SiO₂; latency-optimized memory subsystem; microprocessor design; microprocessor implementation; power management support; reliability availability and serviceability; silicon-on-insulator technology; simultaneous multithreading; Clocks; Costs; Delay; Fabrics; Frequency; Integrated circuit interconnections; Microprocessors; Surface-mount technology; Switches; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332591

Filename

1332591