A dual-core 64 b UltraSPARC microprocessor for dense server applications

Author

Takayanagi, T. ; Shin, Jinuk Luke ; Petrick, Bruce ; Su, Jianhui ; Levy, Hanoch ; Pham, Hieu ; Son, Junggab ; Moon, N. ; Singh, Monika ; Mathur, Vinita ; Leon, Ana Sonia

Author_Institution

Sun Microsystems, Sunnyvale, CA, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

58

Abstract

A processor core, previously implemented in a 0.25 μm Al process, is redesigned for a 0.13 μm Cu process to create a dual-core processor with 1 MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise are discussed.

Keywords

cache storage; copper; integrated circuit design; integrated circuit interconnections; integrated circuit noise; integrated memory circuits; leakage currents; microprocessor chips; network servers; thermal stability; 0.13 micron; 0.25 micron; 1 Mbit; 64 bit; Al; Al process; Cu; Cu process redesign; NBTI; circuit design challenges; compute-dense server applications; coupling noise; dense server applications; dual-core UltraSPARC microprocessor; leakage; negative bias temperature instability; performance/power ratio; processor core; processor integrated L2 cache; Circuit noise; Computer networks; Delay; Impedance; Microprocessors; Moon; Network servers; Niobium compounds; Titanium compounds; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332592

Filename

1332592