Title :
A 40 Gb/s network processor with PISC™ dataflow architecture
Author :
Carlström, Jakob ; Nordmark, Gunnar ; Roos, Joachim ; Bodén, Thomas ; Svensson, Lars-Olof ; Westlund, Pär
Author_Institution :
Xelerated AB, Stockholm, Sweden
Abstract :
This 40 Gb/s network processor has a dataflow architecture with 200 PISC™ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 μm CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.
Keywords :
CMOS integrated circuits; electronic switching systems; instruction sets; integrated circuit design; integrated circuit interconnections; microprocessor chips; packet switching; telecommunication equipment; telecommunication network routing; 0.13 micron; 200 MHz; 40 Gbit/s; 9.5 W; CMOS process; I/O processors; PISC dataflow architecture; PISC processor linear array; network processor; off-chip engine interconnection; on-chip engine interconnection; packet instruction set computer; power dissipation; Clocks; Computer architecture; Coprocessors; Engines; Ethernet networks; Pipelines; Process design; Protocols; Registers; VLIW;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332593
