DocumentCode
3411442
Title
A scalable X86 CPU design for 90 nm process
Author
Schutz, J. ; Webb, C.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
62
Abstract
A third generation Pentium®4 processor is designed to meet the challenges of a 90 nm technology. Design methodology allows scalability with increased transistor performance over the life of the process. Improved design for test techniques are developed to facilitate the debug process. We also discuss improved design automation techniques to reduce hand-drawn schematics.
Keywords
circuit CAD; design for testability; integrated circuit design; microprocessor chips; nanoelectronics; 90 nm; debug process; design automation techniques; design for test techniques; design methodology; design scalability; hand-drawn schematics; nanoscale technology; scalable X86 CPU design; third generation Pentium 4 processor; transistor performance; Clocks; Delay; Frequency; Integrated circuit interconnections; Leakage current; Process design; Protocols; Registers; Signal processing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332594
Filename
1332594
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