A Novel BIST Architecture for Backplane Interconnect Test

Backplane is a common way for inter-board connection. Faults can be incidentally introduced whenever a board is removed or replaced or added. Thus, backplane interconnect test is an important process to verify a system´s structural correctness. In this paper, we propose a novel BIST architecture for backplane interconnect test in a boundary scan environment. The most significant characteristic of our BIST is adding an ASC (assistant scan chain) unit, which provides a solution for reducing test time, decreasing test complexity and accommodating dynamic backplane configuration. The test process and test algorithms dependant of the proposed BIST are also presented.