• DocumentCode
    3411476
  • Title

    A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

  • Author

    Wendell, D. ; Lin, J. ; Kaushik, P. ; Seshadri, S. ; Wang, A. ; Sundararaman, V. ; Wang, P. ; McIntyre, H. ; Kim, S. ; Hsu, W. ; Park, H. ; Levinsky, G. ; Lu, J. ; Chirania, M. ; Heald, R. ; Lazar, P.

  • Author_Institution
    Sun Microsystems, Sunnyvale, CA, USA
  • fYear
    2004
  • fDate
    15-19 Feb. 2004
  • Firstpage
    66
  • Abstract
    A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm2.
  • Keywords
    CMOS memory circuits; cache storage; microprocessor chips; reduced instruction set computing; 1.6 GHz; 4 MB; 90 nm; CMOS process; RISC microprocessor; SPARC microprocessor; column-redundant elements; high-end servers; next-generation CPU; on-chip L2 cache; reliability mechanism; transistor leakage; Central Processing Unit; Circuits; Clocks; Decoding; Delay; Error correction codes; Microprocessors; Registers; Throughput; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8267-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2004.1332596
  • Filename
    1332596
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3411476