• DocumentCode
    3411556
  • Title

    Using CHARM-2 wafers to increase reliability in ion implant processing

  • Author

    Bammi, Rahul ; Reno, Steven E.

  • Author_Institution
    Nat. Semicond. Corp., West Jordan, UT, USA
  • fYear
    1995
  • fDate
    22-25 Oct. 1995
  • Firstpage
    11
  • Lastpage
    17
  • Abstract
    This paper describes the use of CHARM-2 charge monitor wafers as a BIR (building-in-reliability) tool to identify, monitor and ultimately reduce implanter charging levels, resulting in increased die yields and enhanced product and equipment reliability. An ion implant engineering group at National Semiconductor Corporation has actively used CHARM-2 wafers to quantify charge potential levels existing in high current ion implanters, to baseline and monitor their set of four high current implanters, and to correlate die-level charging patterns on CHARM-2 wafers to product wafer yield patterns. CHARM-2 wafers have been successfully used to determine the effects of implanter equipment modifications and process changes on wafer charging. These equipment modifications have resulted in reduced wafer charging levels, and have therefore, helped to resolve charging-related product yield and reliability issues. The equipment and process modifications implemented with the aid of CHARM-2 wafers have also resulted in significantly improved equipment reliability and increased process robustness. Because of the consistently high degree of correlation of CHARM-2 charging patterns to product wafer yield patterns, CHARM-2 wafers serve as an effective in-line, implant charge monitor in a manufacturing environment.
  • Keywords
    charge measurement; integrated circuit measurement; integrated circuit reliability; integrated circuit yield; ion implantation; reliability; CHARM-2 wafers; building-in-reliability; charge monitor wafers; charge potential levels; die yields; die-level charging patterns; equipment reliability; ion implant processing; manufacturing environment; process robustness; product reliability; product wafer yield patterns; product yield; reliability; wafer charging levels; EPROM; Implants; Manufacturing processes; Monitoring; Semiconductor device reliability; Sensor arrays; Sensor phenomena and characterization; Substrates; Surface charging; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop, 1995. Final Report., International
  • Conference_Location
    Lake Tahoe, CA, USA
  • Print_ISBN
    0-7803-2705-5
  • Type

    conf

  • DOI
    10.1109/IRWS.1995.493568
  • Filename
    493568