Passivation scheme impact on retention reliability of non volatile memory cells

Non Volatile Memory cells must retain the data (i.e. the charge stored in the floating gate) during the device lifetime, typically at least 10 years. In this work we study the impact of different passivation layers on the data retention of single polysilicon EEPROM cells, processed with an advanced 0.7 /spl mu/m process technology. Three passivation layers have been considered: (1) Phosphorus doped Silicon Glass (PSG), (2) Planarized (Oxynitride/SOG/Oxynitride/PSG), and (3) UV-Nitride. Accelerated tests were performed at high temperature (250-350/spl deg/C) up to 500 hours in order to monitor the threshold voltage shift of the floating gate transistor programmed either in the written or in the erased state. In the case of planarized passivation and of UV-nitride passivation the charge loss is small and it largely fulfils the data retention requirements; in the case of PSG passivation a much higher charge loss is observed. The effect of tunnel oxide degradation after extended cycling (1 Mcycles) has been investigated. No significant difference has been found after 200 hours at 250/spl deg/C between cycled and one time programmed cells, evidencing that the charge loss mechanism does not involve tunnel oxide degradation. The activation energy of the charge loss mechanism has been evaluated in the case of planarized passivation, using written cells. The measured value is 1.84 eV. The impact of different passivation schemes was studied with conventional techniques, the best results were obtained with the planarized passivation stack and with the UV-nitride layer.