Title :
ΣΔ ADC with finite impulse response feedback DAC
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
A continuous-time 1 b ΣΔ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 μm CMOS chip consumes 6.0 mW.
Keywords :
CMOS integrated circuits; FIR filters; circuit feedback; clocks; continuous time filters; digital-analogue conversion; integrated circuit design; integrated circuit noise; sigma-delta modulation; timing jitter; ΣΔ ADC; 0.18 micron; 1 MHz; 1 bit; 6.0 mW; CMOS chip; FIRDAC; IM2; IM3; S/N ratio; bandwidth; clock jitter susceptibility; continuous-time sigma-delta ADC; feedback path; finite impulse response DAC; linearity; Bandwidth; Circuit noise; Clocks; Feedback; Filters; Jitter; Linearity; Quantization; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332601
