DocumentCode
3411732
Title
A 3.2 to 4 GHz, 0.25 μm CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN
Author
Terrovitis, M. ; Mack, Michael ; Singh, Kalwant ; Zargari, Masoud
Author_Institution
Atheros Commun., Sunnyvale, CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
98
Abstract
A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 μm standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 μs.
Keywords
CMOS integrated circuits; IEEE standards; frequency synthesizers; integrated circuit measurement; integrated circuit noise; phase noise; telecommunication standards; transceivers; wireless LAN; 0.25 micron; 150 mus; 3.2 to 4 GHz; 5 GHz; CMOS frequency synthesizer; IEEE 802.11a/b/g WLAN; IEEE 802.11a/b/g transceiver; frequency offset; noise spurs; phase noise; settling time; standard CMOS technology; transmitter output; Capacitors; Filters; Frequency synthesizers; Inductors; Phase frequency detector; Phase noise; Tuning; Voltage control; Voltage-controlled oscillators; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332612
Filename
1332612
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