A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation

Author

Martínez-Peiró, Marcos ; Valls, Javier ; Sansaloni, T. ; Pascual, A.P. ; Boemo, E.I.

Author_Institution

Dept. Ingenieria Electron., Valencia Univ., Spain

Volume

1

fYear

1999

fDate

1999

Firstpage

241

Abstract

In this paper, several bit-serial, high-order implementations of cascade, lattice and direct-form FIR filters using Distributed Arithmetic (DA) are studied. Although lattice and cascade structures present many interesting properties related to quantification error and stability, the DA versions have not been thoroughly compared. Three types of filters with their particular bit-serial DA model error have been built using an ALTERA 10K50 FPGA and their area-time figure is analysed. The results show that a 60th order bit-serial cascade and direct-form implementation at nearly 4 MHz and a 40th order lattice structure at 7.5 MHz can be implemented. Moreover, the lattice filter presents the lower quantification error

Keywords

FIR filters; cascade networks; circuit stability; distributed arithmetic; field programmable gate arrays; lattice filters; roundoff errors; 4 MHz; 7.5 MHz; ALTERA 10K50 FPGA; FIR filter structure comparison; FPGA bit-serial distributed arithmetic implementation; area-time figure; bit-serial DA model error; cascade FIR filters; direct-form FIR filters; lattice FIR filters; quantification error; stability; Arithmetic; Bandwidth; Digital signal processing; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Lattices; Pipeline processing; Resource management; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812268

Filename

812268