• DocumentCode
    3412040
  • Title

    How scaling will change processor architecture

  • Author

    Horowitz, Mark ; Dally, W.

  • Author_Institution
    Stanford Univ., CA, USA
  • fYear
    2004
  • fDate
    15-19 Feb. 2004
  • Firstpage
    132
  • Abstract
    For the past 30 years processors have hidden scaling from the programmer, presenting the same sequential computational interface. Power and wire scaling issues are causing this interface to change, exposing more parallelism. For efficiency, future machines must be distributed and heterogeneous and will add at least a "stream" programming interface.
  • Keywords
    instruction sets; microprocessor chips; parallel architectures; achievable performance; modular machines; parallelism; power constraints; power scaling; processor architecture; scaling effects; sequential computational interface; stream programming interface; wire scaling; Capacitance; Circuits; Clocks; Costs; Delay; Global communication; Parallel processing; Registers; Voltage; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8267-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2004.1332629
  • Filename
    1332629
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3412040