DocumentCode
3412054
Title
Designing outside rail constraints
Author
Annema, A.J. ; van Langevelde, R. ; Tuinhout, H.
Author_Institution
Twente Univ., Enschede, Netherlands
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
134
Abstract
CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.
Keywords
CMOS analogue integrated circuits; integrated circuit design; leakage currents; low-power electronics; CMOS evolution; active cancellation techniques; analog design; gate-leakage mismatch; lower supply voltages; matching tolerances; rail constraints; scaling technologies; thick-oxide transistors; thin-oxide transistors; CMOS process; CMOS technology; Capacitance; Circuits; Energy consumption; Impedance; Power generation; Power harmonic filters; Rails; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332630
Filename
1332630
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