A high-speed high-resolution CMOS current comparator

Author

Luh, Louis ; Choma, John, Jr. ; Draper, Jeffrey

Author_Institution

Univ. of Southern California, Los Angeles, CA, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

303

Abstract

A high-speed high-resolution CMOS current comparator is presented. A dynamic gain boosting stage is used to maximize the comparator gain while maintaining acceptable power consumption. A PMOS regenerative amplifier together with a source follower stage is used to reduce the comparison time and increase the resolution. The charge kick-back (feedback) effect is minimized by properly resetting a few internal nodes and by using an input stage. This circuit has been implemented in a 1.2 μm CMOS process and achieved 100 nA resolution at a sampling rate up to 110 MHz and 170 nA resolution up to 140 MHz with a single 5 V power supply

Keywords

CMOS analogue integrated circuits; current comparators; high-speed integrated circuits; integrated circuit design; 1.2 micron; 100 to 170 nA; 110 to 140 MHz; 5 V; CMOS current comparator; PMOS regenerative amplifier; charge feedback effect minimization; dynamic gain boosting stage; high-resolution current comparator; high-speed current comparator; source follower stage; Boosting; CMOS process; Circuits; Energy consumption; Feedback; MOS devices; Power supplies; Rails; Sampling methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812283

Filename

812283