Buffer architectures for predictable quality of service at the ATM layer

Providing guaranteed quality of service (QoS) in cell and packet based networks places additional demands upon the design of switch fabrics. This paper considers the application of various fundamental buffering approaches in ATM, for support of predictable QoS. The paper identifies the functional requirements of the switch fabric at the ATM layer, and make recommendations for an improved architecture that considers QoS at the switch fabric level. The relative merits of each buffering scheme has been determined by applying realistic broadband traffic loads involving CBR, VBR and UBR traffic to simulated models of the buffer strategies. Simulation results are presented, along with a performance analysis for each scheme. The resultant architecture allows switches to be realised which have reliable and predictable parameters in the ATM layer and which guarantee QoS as well as reducing connection admission control complexity