DocumentCode
3412111
Title
A 160Gb/s interface design configuration for multichip LSI
Author
Ezaki, T. ; Kondo, K. ; Ozaki, Hiroaki ; Sasaki, Naoki ; Kitano, Masao ; Tanaka, Shoji
Author_Institution
Sony, Japan
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
140
Abstract
The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced. 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance. Both the CPU and memory are fabricated in a 0.15μm CMOS technology.
Keywords
CMOS digital integrated circuits; DRAM chips; embedded systems; integrated circuit layout; integrated circuit packaging; large scale integration; low-power electronics; multichip modules; system-on-chip; 123 MHz; 160 Gbit/s; CMOS technology; DRAM; SoC technology; chip layout; embedded CPU; high data transfer rate; interface design configuration; low power consumption; microbumps; multichip LSI; signal interface performance; Bonding; Capacitance; Central Processing Unit; Circuit testing; Clocks; Costs; Flip chip; Large scale integration; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332633
Filename
1332633
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