Title :
A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)
Author :
Miura, Naruhisa ; Sakura, Tamaki ; Kuroda, Tadahiro
Abstract :
A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.
Keywords :
CMOS integrated circuits; SPICE; VLSI; chip scale packaging; equivalent circuits; inductors; integrated circuit design; integrated circuit interconnections; timing jitter; transceivers; 1.2 Gbit/s; CMOS technology; SPICE simulation; VLSI chip; chip-to-chip communications; equivalent circuit; inductive coupling; inductive interchip signaling; linear-logarithmic image; metal spiral inductors; nonreturn-to-zero signaling; sense-amplifying flip-flop; stacked chips; timing constraints; transceiver circuits; wireless bus; wireless superconnect; Coupling circuits; Inductors; Integrated circuit interconnections; Low pass filters; Magnetic analysis; Packaging; Protection; Three-dimensional integrated circuits; Transmitters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332634
