Title :
A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform
Author :
Kangmin Lee ; Se-Joong Lee ; Sung-Eun Kim ; Hye-Mi Choi ; Donghyun Kim ; Sunyoung Kim ; Lee, Min-wuk ; Hoi-Jun Yoo
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18μm 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; packet switching; quality of service; system-on-chip; telecommunication network routing; 1.6 GHz; 1.6 V; 51 mW; CMOS technology; FPGA; SRAM; crossbar partial activation; crossbar switch; globally asynchronous mode; heterogeneous intellectual properties; hierarchical star-connected network; locally synchronous mode; low swing signaling; low-power heterogeneous SoC platform; off-chip gateway; on-chip network; peripheral circuits; portable multimedia SoC; programmable clocking; programmable power management unit; quality of service requirements; serialized low-energy transmission coding; Bandwidth; Clocks; Delay; Energy consumption; Fabrics; Network-on-a-chip; Quality of service; Switches; Tiles; Wires;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332639
