Title :
Mixed body-bias techniques with fixed Vt and Ids generation circuits
Author :
Sumita, M. ; Sakiyama, S. ; Kinoshita, Moto ; Araki, Yuichi ; Ikeda, Yasuhiro ; Fukuoka, Kazuki
Author_Institution :
Matsushita Electr. Ind., Nagaokakyo, Japan
Abstract :
In sub-1V CMOS VLSIs, body-bias generation circuits are proposed in which Ids,, and Vt, of PMOS/NMOS are always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, an 85% reduction of the delay variation, and a 75% improvement in the power consumption of an SRAM on a mobile processor.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; VLSI; integrated circuit design; low-power electronics; microprocessor chips; CMOS VLSI; SRAM; body-bias generation circuits; correlation diagram; delay variation; domino circuits; low power; mixed body-bias techniques; mobile processor; positive temperature dependence; power consumption; readout circuit; CMOS process; CMOS technology; Circuit testing; Intrusion detection; MOS devices; Radio frequency; Random access memory; Semiconductor device measurement; Temperature; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332642
