Title :
A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS
Author :
Mathew, Sanu ; Anders, Mark ; Bloechel, B. ; Nguyen, Thin ; Krishnamurthy, Ram ; Borkar, Shekhar
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A 64b integer execution ALU is described for 4GHz single-cycle operation with a 32b mode ALU latency of 7GHz. The 0.073mm2 chip is fabricated in a 90nm dual-V, CMOS technology and dissipates 300mW. Sparse-tree adder architecture, single-rail dynamic circuits, and a semidynamic implementation enable a 20% performance improvement and a 56% energy reduction compared to a Kogge-Stone implementation.
Keywords :
CMOS logic circuits; adders; microprocessor chips; nanoelectronics; 300 mW; 4 GHz; 64 bit; 90 nm; ALU latency; Kogge-Stone implementation; adder critical path; carry-merge logic; dual supply voltages; dual-V CMOS technology; efficient power-performance trade-off; energy reduction; fully-static conditional sum generators; integer execution ALU; semidynamic implementation; single-cycle operation; single-rail dynamic circuits; sparse-tree adder architecture; superscalar microprocessor execution cores; Active noise reduction; Adders; CMOS technology; Circuit noise; Delay; Multiplexing; Phase noise; Power measurement; Stress measurement; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332644
