Multinet switch: multistage ATM switch architecture with partially shared buffers

An asynchronous transfer mode (ATM) switch architecture, the multinet switch, is presented. It is a self-routing multistage switch with internal buffers capable of achieving 100% throughput. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric, thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partial buffer sharing discipline. In a partial buffer sharing scheme, buffers are partially to accommodate bursty traffic and to limit the performance degradation that may happen in a completely shared system where a small number of calls ties up the entire buffer space unfairly. Although the hardware complexity is similar to that of the input queueing switches, the multinet switch has throughput and delay performance similar to that of output queueing switches without the hardware complexity. A simple extension of the multinet switch to handle multiple priority traffic and multicast traffic is proposed