A fully integrated 0.13 μm CMOS 10 Gb Ethernet transceiver with XAUI interface

Author

Hyung-Rok Lee ; Moon-Sang Hwang ; Bong-Joon Lee ; Young-Deok Kim ; Dohwan Oh ; Jaeha Kim ; Sang-Hyun Lee ; Deog-Kyoon Jeong ; Wonchan Kim

Author_Institution

Seoul Nat. Univ., South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

170

Abstract

A 10 Gb Ethernet transceiver chip integrated with 10 Gb/s serial and quad 3.125 Gb/s XAUI interfaces is implemented in 0.13 μm CMOS and dissipates 898 mW from 1.2 V. A digital coarse control algorithm for VCOs reduced the VCO gains for noise immunity. A blind oversampling technique enabled synthesis of the XAUI interface.

Keywords

CMOS integrated circuits; integrated circuit noise; local area networks; network interfaces; signal sampling; transceivers; voltage-controlled oscillators; 0.13 micron; 1.2 V; 10 Gbit/s; 3.125 Gbit/s; 898 mW; Ethernet transceiver chip; XAUI interface synthesis; blind oversampling technique; digital coarse control algorithm; fully integrated CMOS Ethernet transceiver; noise immunity; power dissipation; quad XAUI interfaces; reduced VCO gain; serial interfaces; CMOS technology; Clocks; Ethernet networks; Frequency locked loops; Phase frequency detector; Phase locked loops; Transceivers; Tuning; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332648

Filename

1332648