DocumentCode
341240
Title
A new approach for testing MOS circuits based on large defects
Author
Rauscher, Reinhard ; Schütz, Bernd
Author_Institution
Dept. of Comput. Sci., Hamburg Univ., Germany
Volume
2
fYear
1999
fDate
1999
Firstpage
838
Abstract
This work presents a new approach for testing MOS circuits. The proposed model is based on the idea that for each kind of fault a dedicated set of test patterns can be generated. In particular for the case of large defects, we defined a dedicated fault model and suggested an approach for detecting such defects with a minimum amount of patterns
Keywords
CMOS logic circuits; VLSI; automatic test pattern generation; fault simulation; integrated circuit testing; logic testing; ATPG; CMOS VLSI; MOS circuit testing; dedicated fault model; dedicated set of test patterns; fault oriented analysis; large defects; minimum amount of patterns; pseudo code; stuck at faults; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Costs; Electrical fault detection; Fault detection; Shape; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 1999. IMTC/99. Proceedings of the 16th IEEE
Conference_Location
Venice
ISSN
1091-5281
Print_ISBN
0-7803-5276-9
Type
conf
DOI
10.1109/IMTC.1999.776983
Filename
776983
Link To Document