Title :
A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR
Author :
Ohtomo, Y. ; Kawamura, Toshihiko ; Nishimura, Kosuke ; Nogawa, Masafumi ; Koizumi, Hirotaka ; Togashi, Minoru
Author_Institution :
NTT Microsystern Integration Labs., Atsugi, Japan
Abstract :
Implemented in a 0.13 μm CMOS process, pulse pattern generation and BER test functions are integrated in a chip. A parallel CDR (clock data recovery) circuit provides 12.5 Gb/s operation and wide tolerance of over 0.5 UIpp for 4 to 80 MHz sinusoidal jitter.
Keywords :
CMOS integrated circuits; error statistics; phase detectors; pulse generators; synchronisation; telecommunication equipment testing; timing jitter; 0.13 micron; 12.5 Gbit/s; 4 to 80 MHz; BER test functions; BERT; CMOS; PPG; clock data recovery circuit; jitter-tolerant parallel CDR; phase detector; pulse pattern generation; sinusoidal jitter; telecommunications testers; Bandwidth; Bit error rate; Capacitance; Circuits; Clocks; Detectors; Jitter; Large scale integration; Phase detection; System testing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332650
