DocumentCode
3412449
Title
A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18 μm CMOS
Author
Jeongsik Yang ; Jinwook Kim ; Sangjin Byun ; Conroy, C. ; Beomsup Kim
Author_Institution
Berkana Wireless, Campbell, CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
176
Abstract
This paper presents a quad-channel serial-link transceiver which provides 12.5 Gb/s full duplex raw data rate for a single 10 Gb XAUI interface. A mixed-mode LMS adaptive equalizer is adopted, which achieves 3 dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64 ps-pp jitter. The IC consumes 718 mW at 3.125 Gb/s/ch with full duplex data rate.
Keywords
CMOS integrated circuits; adaptive equalisers; computer interfaces; least mean squares methods; synchronisation; timing jitter; transceivers; 0.18 micron; 12.5 Gbit/s; 3.125 Gbit/s; 718 mW; CMOS; LMS adaptive equalizer; XAUI interface; delay-immune CDR circuit; extended attachment unit interface; full duplex raw data rate; mixed-mode adaptive equalizer; quad-channel serial-link transceiver; receive clock jitter; Adaptive equalizers; Circuits; Clocks; Delay; Jitter; Least squares approximation; Multiplexing; Signal generators; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332651
Filename
1332651
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