• DocumentCode
    3412523
  • Title

    A high performance architecture for rotating decimal coordinates

  • Author

    Sanchez, Jose-Luis ; Mora, Higinio ; Mora, Jeronimo ; Jimeno, Antonio

  • Author_Institution
    Comput. Technol. Dept., Univ. of Alicante, Alicante
  • fYear
    2008
  • fDate
    June 30 2008-July 2 2008
  • Firstpage
    1757
  • Lastpage
    1762
  • Abstract
    Although radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are still under development. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to produce fast rotations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Finally, the results with regard to delay obtained by means of an FPGA implementation of the method are shown.
  • Keywords
    digital arithmetic; field programmable gate arrays; BCD operands; CORDIC method; FPGA implementation; decimal arithmetic; decimal coordinates; high performance architecture; radix-10 arithmetic; Calculators; Computer architecture; Databases; Delay; Digital arithmetic; Field programmable gate arrays; High performance computing; Humans; Instruments; Proposals;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics, 2008. ISIE 2008. IEEE International Symposium on
  • Conference_Location
    Cambridge
  • Print_ISBN
    978-1-4244-1665-3
  • Electronic_ISBN
    978-1-4244-1666-0
  • Type

    conf

  • DOI
    10.1109/ISIE.2008.4677157
  • Filename
    4677157