Title :
Design of low power pulsed flip-flop using sleep transistor scheme
Author :
Rao, G. Mareswara ; Rajendar, S.
Author_Institution :
Vardhaman Coll. of Eng., Hyderabad, India
Abstract :
In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm low clock load dynamic flip-flops, a novel sleep transistor scheme is proposed. The scheme is implemented using CMOS 90nm technology file in Synopsis HSPICE. As compared to the conventional pulse triggered flip-flops, the proposed sleep transistor based P-FF design features best power-delay-product performance. The average power and leakage power is reduced without degrading the overall performance.
Keywords :
CMOS integrated circuits; flip-flops; logic design; low-power electronics; transistor circuits; CMOS technology; HSPICE; leakage robustness; low clock load dynamic flip flops; low power pulsed flip flop; power delay product performance; size 90 nm; sleep transistor scheme; Clocks; Delays; Flip-flops; Power demand; Switches; Switching circuits; Transistors; leakage power; power-delay-product; pulse triggered flip-flop; sleep transistor;
Conference_Titel :
Advances in Electrical Engineering (ICAEE), 2013 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4799-2463-9
DOI :
10.1109/ICAEE.2013.6750359
